Recently, a portable telephone or a personal digital terminal is rapidly developing into a comprehensive information appliance by incorporating various functions. To realize multiple functions in a limited volume, the primary demands are reduction of size and enhancement of performance of various devices such as semiconductor chips. However, even in a highly integrated semiconductor chip, it is now becoming difficult to enhance the performance dramatically in the existing method from the viewpoint of cost and technology.
At the present, therefore, there is a mounting demand for high-density mounting technology for housing devices in a compact size.
For higher integration of devices, evolution from two-dimensional wiring to three-dimensional wiring is demanded to satisfy the requests for fine device wiring. An essential point in development lies in how to form a three-dimensional circuit board at a higher density and in a simpler process.
A conventional art includes a printed circuit board in a three-dimensional circuit board structure generally as shown in FIG. 29A to FIG. 29C (see, for example, patent document 1).
A conventional printed circuit board of laminated structure consisting of four layers is briefly described below.
FIG. 29A to FIG. 29C are partial perspective views showing an essential structure of a conventional printed circuit board of laminated structure consisting of four layers, and its manufacturing method.
First, as shown in FIG. 29A to FIG. 29C, on one side of resin film 4010, for example, three one-sided conductor films 4050, having conductor patterns 4020 formed by printing conductive paste, and conductive vias 4030 having via holes filled with conducive paste, are formed. Lands 4040 are formed on conductor patterns 4020 for allowing a positional deviation from conductive vias 4030 when laminating one-sided conductor films 4050.
As shown in FIG. 29B, three one-sided conductor films 4050 are mounted by adjusting the positions of conductor patterns 4020 and conductive vias 4030. From above and beneath three one-sided conductor films 4050, by heating and pressing by using, for example, a press machine, printed circuit board 4000 of four-layer structure is formed as shown in FIG. 29C.
By photo-forming method, a manufacturing method of a wiring board having a three-dimensional circuit board structure is disclosed (see, for example, patent document 2).
Referring now to FIG. 30 and FIG. 31A to FIG. 31E, a manufacturing method of a wiring board having a three-dimensional circuit board structure by photo-forming method is described below.
FIG. 30 is a sectional view schematically showing a manufacturing apparatus of wiring board, and FIG. 31A to FIG. 31E are sectional views explaining a manufacturing method of wiring board by using the manufacturing apparatus in FIG. 30.
As shown in FIG. 30, manufacturing apparatus 4100 of wiring board has first reserve tank 4120 containing insulating liquid resin 4110, and second reserve tank 4140 containing conductive liquid resin 4130. It also has moving control unit 4180 for moving board 4160 placed on table 4150 alternately between first reverse tank 4120 and second reserve tank 4140. Further, insulating liquid resin 4110 or conductive liquid resin 4130 on board 4160 placed at a specified depth is cured by scanning a specified pattern by using laser irradiation device 4190 for generating an ultraviolet ray or the like, and a specified pattern is formed by photo-forming method.
A specific manufacturing method is explained by referring to FIG. 31A to FIG. 31E.
First, as shown in FIG. 31A, board 4160 is immersed in insulating liquid resin 4110 in first reserve tank 4120, and electric insulating layer 4200 is formed in a specified thickness on the surface of board 4160 by photo-forming method.
Next, as shown in FIG. 31B, board 4160 is immersed in conductive liquid resin 4130 in second reserve tank 4140, and after conductive liquid resin 4130 is flattened to a specified thickness, specified conductor pattern 4210 is formed on electric insulating layer 4200 by photo-forming method. By removing conductive liquid resin 4130 except for conductor pattern 4210, a first layer of conductor pattern 4210 is formed.
As shown in FIG. 31C, board 4160 is immersed in insulating liquid resin 4110 in first reserve tank 4120, and electric insulating layer 4220 is formed in a specified thickness on conductor pattern 4210 of board 4160 by photo-forming method. At this time, light is not emitted to a specified position of insulating liquid resin 4110 on conductor pattern 4210, and insulating liquid resin 4110 is removed, so that via hole 4230 is formed.
As shown in FIG. 31D, board 4160 is immersed in conductive liquid resin 4130 in second reserve tank 4140, and after conductive liquid resin 4130 is flattened to a specified thickness, a second layer of conductor pattern 4240 for covering via hole 4230 is formed on electric insulating layer 4220 by photo-forming method.
Finally, as shown in FIG. 31E, by the same method as mentioned above, electric insulating layer 4230 and a third layer of conductor pattern 4260 are formed on conductor pattern 4240.
In this process, it is explained by a wiring board of multiple layers can be formed at high productivity.
Another example is about forming a three-dimensional structure by photo-forming method by using a liquid crystal mask (see, for example, patent document 3).
According to this method, by using a liquid crystal mask, a three-dimensional shape of a desired structure formed of photosetting resin is integrally formed by a non-laminating layer, and plural components of different shapes can be manufactured at the same time, and it is suited to production of multiple variety and small quantity.
Similarly, by photo-forming method, a manufacturing method of circuit parts by forming an electric circuit pattern in a three-dimensional structure is disclosed (see, for example, patent document 4).
According to the method, as shown in FIG. 32, by photo-forming method, three-dimensional structure 4300 is formed by curing a photosetting resin in layers. Metal plating is formed on the surface, and electric circuit pattern 4310 is formed from the metal plating by using photolithography or etching method. As a result, electric circuit pattern 4310 is formed on three-dimensional structure 4300 in a short time, and circuit parts are obtained.
However, in the printed circuit board in patent document 1, conductor patterns are formed on upper and lower sides of a plurality of resin films, and are connected to conductive vias formed in the resin films, and thereby a laminated board is formed. At this time, in consideration of deviation in connection positions of conductive vias and conductor patterns when laminating the resin films, lands are formed.
As a result, the following problems are caused as shown in FIG. 33A and FIG. 33B.
FIG. 33A and FIG. 33B are schematic diagrams explaining a connected state of conductive vias 4030 and conductor patterns 4020 by way of lands 4040.
That is, as shown in a plan view in FIG. 33B, due to lands 4040 to be connected to conductive vias 4030, conductor patterns 4020 must be disposed by evading the locations of lands 4040, and conductor patterns 4020 cannot be formed at fine pitches.
Besides, since conductor patterns 4020 can be formed only on both side of resin films, three-dimensional wiring of high density is limited.
Since conductive vias 4030 and conductor patterns 4020 are connected by compressing or bonding, due to entry of foreign matter or forming of oxide film on the connection interface, the connection resistance may be increased, or the connection reliability may not be satisfactory. To avoid such troubles, if the interface is processed by etching or the like, the number of processes is increased, and the productivity may be lowered.
When a plurality of resin films are laminated and integrated, due to remaining bubbles or the like, peeling is likely to occur, and the reliability may be inferior.
Similarly, in the wiring board in patent document 2, the conductor patterns and the electric insulating layers are formed by changing over the reserve tanks, the wiring bard of multiple-layer structure can be manufactured easily.
However, in this wiring board, too, since the conductor patterns are larger than the shape of conductive vias, conductor patterns of fine pitches cannot be formed.
Besides, since the conductor patterns are formed on the flatly formed electric insulating layer, conductor patterns cannot be formed at desired positions.
Yet, since the conductor patterns, conductive vias, and electric insulating layers are formed in separate processes in each layer, the productivity is lowered, and the reliability is connection is not satisfactory between layers of conductor patterns and conductive vias.
According to patent document 3, a three-dimensional insulating structure can be manufactured in batch, but nothing specific is disclosed about the electrically connected three-dimensional wiring electrodes.
The circuit parts disclosed in patent document 4 are intended to form electric circuit patterns at specified positions on the surface of a three-dimensional structure.
It is hence difficult to form electric circuit patterns having a three-dimensional structure. Moreover, since the electric circuit patterns are formed by etching, it is difficult to form finely in steps of three-dimensional structure, and the productivity is lower.    Patent document 1: Unexamined Japanese Patent Publication No. 2002-368418    Patent document 2: Unexamined Japanese Patent Publication No. 2004-22623    Patent document 3: Unexamined Japanese Patent Publication No. 2001-252986    Patent document 4: Unexamined Japanese Patent Publication No. 10-12995